Method and system for soft programming algorithm

ABSTRACT

A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell&#39;s bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to floating gate memory devices, such as flashmemory, and in particular to methods and circuits for repairingover-erased floating gate memory cells.

2. Description of Related Art

Non-volatile memory design based on integrated circuit technologyrepresents an expanding field. Several popular classes of non-volatilememory are based on arrays of floating gate memory transistors which areelectrically erasable and programmable.

The act of programming a memory array of floating gate memorytransistors in one popular approach involves injecting the floating gateof addressed cells with electrons which causes a negative charge toaccumulate in the floating gate and the turn-on threshold of the memorycell to increase. Thus, when programmed, the cells will not turn on,that is, they will remain nonconductive when addressed with readpotentials applied to the control gates. The act of erasing a cellhaving a negatively charged floating gate involves removing electronsfrom the floating gate to lower the threshold. With the lower threshold,the cell will turn on to a conductive state when addressed with a readpotential to the control gate. For an opposite polarity array,programming involves selectively removing electrons from the addressedcells' floating gates.

Floating gate memory cells suffer the problem of over-erasure.particularly when erasing involves lowering the threshold by removingelectrons from the floating gate. During the erase step, over-erasureoccurs if too many electrons are removed from the floating gate leavinga slight positive charge. The positive charge biases the memory cellslightly on, so that a small current may leak through the memory evenwhen it is not addressed. A number of over-erased cells along a givendata line can cause an accumulation of leakage current sufficient tocause a false reading.

In addition to causing false readings, when floating gate cells areover-erased, it makes it difficult to successfully reprogram the cellsusing hot electron programming, particularly with embedded algorithms inthe integrated circuits. This difficulty arises because the amount ofelectrons needed to move an over-erased cell to the programmed state islarger than for normal cells.

Further, because the erase and program operations can affect differentcells in a single array differently, floating gate memory designs ofteninclude circuitry for verifying the success of the erasing andprogramming steps. See, for instance, U.S. Pat. No. 4,875,118, entitledVOLTAGE MARGINING CIRCUIT FOR FLASH MEMORY, invented by Jungroth. If thearray does not pass erase verify, the entire array is usually re-erased.The re-erase process can aggravate over-erased cells in the array.

One solution to the over-erase problem associated with the eraseverification process is disclosed in U.S. Pat. No. 5,414,664, FLASHMEMORY WITH BLOCK ERASE FLAGS FOR OVER-ERASURE PROTECTION, issued to Linet al. on May 9, 1995, which shows a method and a device where onlythose blocks which fail the erase verify operation are re-erased.Accordingly, a re-erase of the entire array after each verify operationis not required. This mitigates the over-erase phenomenon, but does notsolve it entirely.

Thus, a repair process has been developed to correct over-erased cells.U.S. Pat. No. 5,233,562, entitled METHODS OF REPAIRING FIELD-EFFECTCELLS IN AN ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE MEMORYDEVICE, issued to Ong, et al., describes processes for such repair usingso called drain disturb, source disturb or gate disturb techniques.After each repair in the Ong patent, a time consuming repairverification operation of the entire array is provided. See, also, U.S.Pat. No. 5,416,738 to Shrivastava for further background information.

In any case, the repair and repair verification processes aretime-consuming. Therefore, a method and device which repairs over-erasedcells in FLASH memory, and other floating gate memory, more quickly andefficiently is needed.

SUMMARY OF THE INVENTION

The present invention incorporates a soft program cycle into an erasesequence for a floating gate memory device, which quickly andefficiently repairs over-erased cells. The process is suitable for usein an embedded erase algorithm for integrated circuit flash memorydevices and for other floating gate memory architectures.

According to the present invention, a segmentable floating gate memoryarray is provided with circuitry for applying a soft program repairpulse to an entire sector of floating gate memory cells in parallel.This technique in combination with a sector by sector erase structure,provides a quick and efficient technique for sector erase with softprogram repair pulses in a floating gate memory device.

Thus, according to one aspect, the invention can be characterized as afloating gate memory integrated circuit which includes an array offloating gate memory cells. The array includes a plurality of sectors,each including a plurality of drain lines coupled to drain terminals inrespective columns of cells in the sector, a plurality of source linescoupled to source terminals in respective columns of cells in thesector, and a plurality of word lines coupled to control gate terminalsof respective rows of cells in the sector. Of course, depending on thearchitecture of the array, a single conductor may act as both a sourceline and drain line between adjacent memory cells. A control circuit iscoupled with the drain lines, source lines and word lines in theplurality of sectors, for setting the threshold voltages of the cells ina selected sector to a low threshold state (erased state) in which thecells have a specified range of threshold voltage. The control circuityincludes voltage supply circuits to supply a voltage sequence to lowerthe threshold of cells in the selected sector which results in somecells having thresholds lowered below the specified range of thresholdvoltages (over-erased). Following the first voltage sequence to lowerthe threshold, a repair pulse is applied to the selected sector. Therepair pulse is applied during a repair time interval such that itinduces a source disturb or a drain disturb soft program effect.

According to one aspect of the invention, the voltage on the word linesis set on a level below the minimum of the specified range of thresholdvoltages, and above ground. Increased word line voltage enhances the hotelectron injection current flowing in the cells subject to the softprogram pulse, and speed up the process. In alternative systems, theword lines may be pulled substantially to ground during the repairpulse. To control disturbance of cells in the array, the word linevoltages in a preferred system are pulled to a level above ground butless than about 0.5 volts during the repair pulse.

According to another aspect of the invention, the control circuitincludes circuitry to drive the word lines during the repair pulse in atwo step sequence. In a first step of the sequence, the word lines aredriven to a first level for a first time interval, and during a secondstep in a sequence, the word lines are driven to a second higher levelfor a second time interval. This two level pulse on the word lines is atechnique for controlling the amount of current consumed during the softprogram cycle. Thus, during the lower voltage first step in thesequence, cells subject to the repair pulse are programmed towards thenormal erase state with a controlled current because of a lower wordline voltage. After the first step, a second higher voltage level isapplied to the word lines. This higher voltage induces greater hotelectron injection current for the balance of the soft program pulse,and more effectively repairs cells within a given amount of time. In apreferred system , the repair time interval will last about 200 ms, withthe word line voltage held at a first lower level of about 0.1 volts for100 ms, and then raised to a second higher level of about 0.4 volts forthe balance of the 200 ms repair pulse interval. Preferably, during thefirst step of the repair pulse, the word line voltage is held at a valueof between ground and about 0.2 volts. During the second step, the valueis held at less than about 0.5 volts and approximately 0.4 volts.

According to the present invention, the repair pulse is applied bydriving the plurality of drain lines in a selected sector in the arrayto a positive voltage, for example of about 5.5 volts, and driving theplurality of source lines substantially to ground. This induces aso-called drain disturb repair pulse. An alternative system may utilizea so-called source disturb repair pulse, which applies a positivevoltage to the source while grounding the drain. Furthermore, thecurrent limiting circuitry may be included on at least one of theplurality of drain lines and the plurality of source lines in thesectors in the array. For example, a current limiting transistor may becoupled to the source lines. This prevents the amount of current of anyparticular sector in the array from consuming the available drive powerof the voltage sources which provide the repair pulse.

Accordingly, the present invention provides an embedded erase algorithmwith a soft program pulse to quickly and efficiently repair over-erasedcells. The pulse is applied sector by sector, or to the entire array inparallel, so that it is accomplished in relatively a short amount oftime available for use in commercial integrated circuits. Furthermore,in a preferred embodiment a two step pulse is provided which allows forsoft programming with a lower voltage on the bit line, for faster softprogramming without disturbing properly erased cells, and manages thecurrent consumed during the soft programming operation.

Other aspects and advantages of the present invention can be seen uponreview of the figures, the detailed description and the claims whichfollow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic block diagram providing an overview of anintegrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a segmented array architecture for afloating gate memory cell device.

FIG. 3 is an overall flow chart of this invention.

FIG. 4 is a more specific flow chart illustrating the sector erase andrepair process of this invention.

FIG. 5 is a circuit diagram showing a word line driver having a twolevel pull down according to this invention.

FIG. 6 is a flow chart illustrating a two stage soft programming processof this invention.

FIG. 7 is a circuit diagram of a three level pull down for a word linedriver according to the present invention.

FIG. 8 is a circuit diagram showing word line driver circuit elementsfor use with the circuit of FIG. 7.

FIG. 9 is a schematic diagram of a top block select driver for applyinga repair pulse according to this present invention.

FIG. 10 is a graph showing effects of soft program pulses according tothe present invention.

DETAILED DESCRIPTION

A detailed description of preferred embodiments of this invention isprovided with reference to the figures. The soft program of thisinventionis preferably part of an embedded erase sequence of a floatinggate memory cell device, such a device including an array of cellsarranged in blocks.The soft program generates pulses for quicklyrepairing over-erased cells block by block, while limiting the amount ofcurrent generated during the process.

FIG. 1 shows the basic structure of a 4 megabyte floating gate memorycell integrated circuit incorporating this invention. The circuitincludes a memory array, generally 1, which is divided into a pluralityof blocks (32blocks in the figure). The segmentable architecture of thememory array allows application of the repair pulse of this invention tocell blocks individually, thus allowing block by block repair ofover-erased cells. The array architecture is described in detail belowwith reference to FIG.

Still referring to FIG. 1, coupled with the array 1 are a read andprogram control circuit, generally 6, and a block erase/erase verify/repair circuit, generally 2. The block erase/erase verify/repair circuit2 is coupled to block erase flags 3. An address counter 4 is includedfor incrementing through memory cells, blocks or the entire array forthe erase/erase verify/repair sequence.

The chip includes command logic 5 which is coupled to the address, data,and other control lines such as the output enable and chip enablesignals.The command logic 5 interprets inputs to set a mode of operationfor the read and program control logic 6 and the block erase/eraseverify/repair circuit 2.

Command logic 5 may be implemented as done in standard floating gatememoryintegrated circuits, such as Am28F020 flash memory chipmanufactured by Advanced Micro Devices, Inc. of Sunnyvale, Calif. withadditional commandsof this invention for cell, block or array erase. Inresponse to commands issued by the command logic 5, an embedded eraseoperation is executed by state machines in the erase/erase verify/repaircircuit 2. The user, through a host CPU or otherwise, supplies addressand data signals to the command logic 5 to indicate a preferred mode ofoperation. The modes executed by erase/erase verify/repair circuit 2include a chip erase mode in which all blocks in the array 1 are to beerased and a block erase modein which selected blocks in the array 1 areto be erased. In response to user input, blocks to be erased areidentified by block or sector erase flags 3 stored on the chip.

FIG. 2 illustrates the details of a segmentable array architecture in adrain-source-drain configuration of the floating gate memory circuit inwhich this invention may be implemented, and like that described U.S.Pat.No. 5,399,891, entitled NON-VOLATILE MEMORY CELL AND ARRAYARCHITECTURE, issued Mar. 21, 1995 which is incorporated by referenceherein. Other array architectures may be used, as well.

The circuit includes a first local bit line 10 and a second local bitline 11 which are implemented by buried diffusion conductors. Also,included isa local virtual ground line 12 implemented by burieddiffusion. A pluralityof floating gate transistors having drains andsources coupled to the localbit lines 10, 11 and local virtual groundline 12. Any number of these floating gate transistors in a single blockmay suffer from over-erasure as a result of the erase step mentionedabove, and in varying degrees.

The drains of the first column of transistors, generally 13, are coupledtothe first local bit line 10, and the drains of the second column oftransistors, generally 14, are coupled to the second local bit line 11.The gates of the floating gate transistors are coupled to word lines WL₀through WL_(N), where each word line (e.g., WL₁) is coupled to the gateof a transistor (e.g., transistor 15) in the first local bit line 10 anda transistor (e.g., transistor 16) in the second local bit line 11. Thetransistors 15 and 16 can be considered a two transistor cell with ashared source diffusion.

The act of charging the floating gate is called the program step for thefloating gate memory cell. This is accomplished on a byte by byte basisthrough hot electron injection by establishing a large positive voltagebetween the gate and the source, such as twelve volts, and a positivevoltage between the drain and the source, such as six volts.

The act of discharging the floating gate is called the erase step forthe floating gate memory cell. This is accomplished through the F-N(Fowler-Nordheim) tunneling mechanism between the floating gate and thesource (source erase) or between the floating gate and the substrate(channel erase). The source erasing is performed by applying a positivebias to the source, such as twelve volts or seven volts, while the gateisgrounded or negatively biased, such as minus seven volts. The channelerasing on a block basis is performed by applying a negative bias to thegate and/or a positive bias to the substrate.

Individual blocks of cells are controlled by select signals, that is,top block select signals TBSEL_(A) and TBSEL_(B) and bottom block selectsignals BBSEL_(A) and BBSEL_(B). The individual control of the blocksprovides the ability to apply a repair pulse to selected local bit lines10 and 11.

Still referring to FIG. 2, a first global bit line 17 and a secondglobal bit line 18 are associated with each drain-source-drain block.The first global bit line 17 is coupled to the source of top blockselect transistor19 through a metal-to-diffusion contact 55. Similarly,the second global bit line 18 is coupled to the source of top blockselect transistor 21 through a metal-to-diffusion contact 56. The drainsof the top block select transistors 19, 21 are coupled to the first andsecond local bit lines 10 and 11, respectively. The gates of the topblock selector transistors 19, 21 are thus controlled by a top blockselect signal TBSEL_(A) on line 23.

In a similar manner, the gate of the bottom block select transistor 65Ais controlled by a bottom block select signal BBSEL_(A) across line 26.Thelocal virtual ground line 12 is coupled to a virtual ground terminalacrossconductor 54A through bottom block selector transistor 65A. Thedrain of the bottom block select transistor 65A is coupled to the localvirtual ground line 12. The source of the bottom block select transistor65A is coupled to the conductor 54A. In this architecture, the conductor54A is aburied diffusion conductor which extends to a metal-to-diffusioncontact 60A at a position displaced horizontally through the array,which providescontact to a vertical metal virtual ground bus 25.

For sense amps and program data in structures, a data line 29 is coupledtothe global bit lines 17 and 18 which extend vertically through thearray torespective column select transistors 70, 71. Thus, the source ofcolumn select transistor 70 is coupled to global bit line 17, the gateof column select transistor 70 is coupled to a column decode signalY_(n0), and the drain of the column select transistor 70 is coupled todata line conductor 29.

The blocks of floating gate memory cells as shown in FIG. 1 areconfigured into a plurality of subarrays as illustrated in FIG. 2 whichillustrates two subarrays within a larger integrated circuit. Thesubarrays are divided generally along dotted line 50 and includesubarray 51A generally above the line 50 and subarray 51B generallybelow the line 50. A first group 52 of cells is laid out in a mirrorimage with a second group 53 of cells along a given bit line pair (e.g.,17, 18). As one proceeds up the bit line pair, the memory subarrays areflipped so as to share virtual ground conductors 54A, 54B (burieddiffusion) and metal-to-metal diffusioncontacts 55, 56, 57, 58. Thevirtual ground conductors 54A, 54B extend horizontally across the arrayto a vertical virtual ground metal line 25 through metal-to-diffusioncontacts 60A, 60B. The subarrays repeat on opposite sides of the metalvirtual ground line 25 so that adjacent subarrays share a metal virtualground line 25. The metal virtual ground line 25 is coupled to arrayground and erase high voltage circuitry. Thus,the subarray layoutrequires two metal contact pitches per column of two transistor cellsfor the global bit lines and one metal contact pitch for the metalground line 25.

During a soft program pulse, driving the word line at slightly highervoltage creates a possibility that a higher current may be generated inthe sector being soft programmed. This current is limited by a currentlimiter circuit on the source side of the cell. With reference to FIG.2, the bottom block select transistor 65B or 65A acts as a currentlimiter. This transistor on its source side is connected to the arrayground power supply, which is a generator to support zero volts or apositive voltage depending on the mode of operation. Thus bottom blockselect transistors 65A, 65B are sector decode transistors which alsoserve as current limiters during soft program. Other current limitingschemes, such as current mirror circuits, could be utilized as well.

The sector decode ability provided by the circuit of FIG. 2, allows thecircuitry to be implemented which applies a drain disturb style softprogram pulse only to selected segments of the array by applying about5.5volts to the local drain lines, while grounding the source.

Also, an alternative system will apply the soft program pulse of about5.5 volts, or more depending on circuit parameters, through the sourceterminal of devices being soft programmed, while grounding the bit linesor drain terminals. The same segment-by-segment decoding, and word linedrivers can be utilized in this source disturb approach.

Referring to FIG. 3, an overall flow chart of a chip or block eraseprocess, including the soft program steps of this invention, is shown.After starting the erase operation (step 80), pre-programming isinitiatedfor the chip or block selected for erase, through a host CPU orotherwise through command logic 5 (step 81). At step 82, a programrecovery period occurs allowing the voltage to settle out or stabilizeafter pre-programming. At step 83, a program verify process occurs. Thesystem then checks to see if the last address in the chip or block hasbeen preprogrammed (step 84). If not, the process starting at thepre-programming step is repeated until all cells in the chip or blockhavebeen preprogrammed.

After pre-programming, the erase operation at step 85 is executed whichis followed by the erase recovery period 86 to allow the erase voltageto settle out. Next, an erase verify operation 87 is performed. Then,the system checks to see if the erase process is complete at step 88. Ifnot, it returns to step 85, performing the erase operation untilcomplete. Whencomplete, the soft program at step 89 is initiated inwhich the soft program pulse is applied to all cells in the entire chipor block subject of the erase operation in parallel. The soft programrecovery occurs at step 90. The process ends at step 91.

FIG. 4 illustrates one embodiment of this invention including analgorithm for the embedded erase and repair process of this inventionwhich is generally executed by the control circuit 2 using the blockerase flags 3 and address counter 4 of FIG. 1. This embodiment maintainsthe word line voltage at ground or preferably slightly above groundduring a 5.5 volt repair pulse across the bit line and the sourceterminals.

According to the embedded erase algorithm, an erase operation begins atstep 99 with the setting of one or more flags indicating sectors of thearray to be erased. For chip erase, all flags are set and the addresscounters are initialized to address zero. If a block erase operation istobe executed, the only flags for selected sectors are set. According tothisembodiment of the present invention, repair flags are also set, onefor each block erase flag, to identify sectors to receive the softprogram repair pulse (step 99A). Next, a pre-program operation isexecuted on selected sectors (step 100).

In the next step, all the sectors having a set flag are erased (step101). During the erase operations, the high voltages of the virtualground line 25 are isolated from the unselected sectors by, for example,the BBSEL transistors. For blocks in the same sector, BBSEL has the samevoltage level. BBSEL is driven with high voltage to pass array highvoltage when the sector flag is set, and with zero volts when the sectorflag is reset.This allows a sectored erase operation. Then the entireset of selected blocks is erased by applying energizing voltages asdescribed above, segmented under control of the bottom block selecttransmitter.

Next, a timer waits for an erase timeout condition (step 102). After thetimeout condition, an erase recovery phase is entered (step 103) Again,this recovery phase is timed as indicated at step 104.

After erase recovery, the erase verify voltages are set up (block 105).This operation is described in detail in U.S. Pat. No. 5,463,586entitled ERASE AND PROGRAM VERIFICATION CIRCUIT FOR NON-VOLATILE MEMORY.

The next step is to evaluate the flag and test the data in each locationinside the blocks having a set flag (block 106). This routine involvesdetermining whether the flag is set (block 107). If it is set, theroutinechecks first for an erase verify pass and overflow of the leastsignificantbit counter (block 108). If a pass is detected and thecounter is not at the end of the block, then the least significant bitaddress is incremented (block 109). At this point, the algorithm loopsback to block 106.

If the flag is not set, then the algorithm loops to block 110 where ittests to determine whether all flags have been reset. If all have beenreset, or are in a reset state at the beginning of the routine, then thealgorithm indicates that the erase is done (block 112). If all flagshave not been reset, then the algorithm loops back to block 101 tore-erase blocks having a set flag.

If, at block 108, a cell did not pass erase verify, or passes but is thelast LSB in the block, then the algorithm branches to block 113. Inblock 113 , the algorithm again tests for erase verify pass and the endof the block. If the cell is at the end of the block and passes, thenthe erase flag for the block is reset (block 114). If the cell is not atthe end of the block the erase flag for the block is not reset at thistime, then theMSB address is incremented to go the next block, and theLSB address is reset (block 115). At that point, the algorithm loopsback to block 106 toloop through other blocks having a set flag forerase verify.

After erase verify, the soft program repair pulse is applied to blockshaving a set repair flag. Thus, the word line voltage is initially setat ground or above, preferably at approximately 0.3 volts (step 113),but maybe more or less. In this embodiment, that word line voltage ismaintained while the repair pulse is applied for approximately 200 ms tothe bit lineto sectors having set repair flags (step 114). Finally, therepair flags are reset without a repair verify operation (step 115).During the repair pulse, top block select transistors of selectedsectors are enabled in response to the repair flags, so that a repairvoltage of 5.5 volts is applied to the buried drain lines to repairthose over-erased cells which reside in the selected sectors (sectorerase case) or the whole chip (chiperase case). The repair pulse mayrange, for example from about 3.5 volts to about 10.0 volts depending onthe channel length and other cell parameters, on the repair pulselength, and on other factors.

FIG. 5 illustrates a word line driver adapted for driving word lines inselected sectors to a value slightly above ground to speed up the softprogram process over implementations in which the word line is pulled toground during a soft program. The circuit in FIG. 5 includes a firstinput501 which is connected to the word line decoder. The signal oninput 501 isconnected through pass transistor MN2 to node 502.Transistor MN2 is biasedon by the voltage VDD connected to its gate.Node 502 is connected to the drain of n-channel transistor MP1. Thesource and n-well of transistor MP1are coupled to the supply AVX. Thegate of p-channel transistor MP1 is connected to the word line 503 (WL).Node 502 is also connected to the gate of p-channel transistor MP2 andthe gate of n-channel transistor MN1.The source of transistor MP2 andthe n-well of transistor MP2 are connectedto the supply voltage AVX. Thedrain of transistor MP2 is connected to the word line 503. The drain oftransistor MN1 is connected to the word line 503. The source oftransistor MN1 is connected to a pull down driver circuit generally 76.

The pull down driver circuit 76 includes an enable soft program ENSPGinput92. Input 92 is connected to the gate of n-channel transistor 93,which hasa width of about three microns and a length of about 100microns. The drainof transistor 93 is connected to the supply VDD andthe source of transistor 93 is connected to node 504. Node 504 isconnected to the gate and drain of n-channel transistor 95 which has awidth of about 4 microns and a length of about 1 micron. The source oftransistor 95 is connected to node 99 which is also connected to thesource of transistor MN1. Node 99 is connected across intrinsicn-channel transistors 94 and 96 to the ground terminal. Intrinsicn-channel transistor 96 has its gate and drain connected to node 99 andits source connected to ground. Transistor 96 hasa width of about 20microns and a length of about 1 micron. Transistor 94 has its drainconnected to node 99 and its source connected to ground. Thegate oftransistor 94 is connected to the output of inverter 505. Transistor 94has a width of about 200 microns and a length of about 1 micron. Theinput of inverter 505 is connected to the enable soft program ENSPGinput 92.

During a soft program process, all word lines are selected by drivingthe input 501 high. This disables the pull up transistor MP2 whileenabling the pull down transistor MN1. As the word line 503 is pulleddown, transistor MP1 pulls up on node 502.

The pull down driver 76 during the enable soft program sequence receivesa high enable soft program signal. This turns on transistors 93, 95, and96,while turning off transistor 94. This creates a voltage divider whichholdsthe word line voltage at node 503 above ground at about 0.3 voltsin this embodiment. When the enable soft program pulse ends, the signalat node 92goes low, turning off transistors 93 and 95, and turning ontransistor 94. Transistor 94 is significantly larger than transistor 96,and pulls node 99 down essentially to the ground potential.

Turning to FIG. 6, another embodiment of this invention is shown. Here,therepair pulse is applied in two sequential steps. In the first step,the word line voltage is maintained at a first level above ground, andin the second step, the word line voltage is maintained at a secondlevel above ground. Preliminarily, steps similar to those of FIG. 4 takeplace. Different, however, is that FIG. 6 shows that during steps 607through 610, the word line voltage is maintained at two different levelswhile therepair pulse is applied to the bit line.

First, step 607 provides that the word line voltage is maintained aboveground, e.g. between 0.1 volts and 0.2 volts, for a period of time, e.g.approximately 100 milliseconds. The first stage of the repair pulse ismaintained during step 608. By first applying a lower word line biasduring the first soft program steps 607 and 608, the current of the"over-erased" cells is less than would occur with higher word linevoltage, yet the majority over-erased cells are pushed toward being"normal cells" (i.e. they recover the threshold voltage to a bettervalue). Thus after the first soft program steps 607 and 608, someover-erased cells have been calibrated and the second step can beapplied.The second steps 609 and 610 include setting the word linevoltage to between approximately 0.4 volts and 0.5 volts, or more orless, which is applied for an additional period of time, e.g.approximately 100 milliseconds while the repair pulse is applied.

Accordingly, during the repair pulse, the word line voltage is driven intwo stages, the first stage occurring during the 100 ms period while theword line voltage is maintained between approximately 0.1 volts and 0.2volts, the second stage occurring during the 100 ms period while theword line voltage is maintained between approximately 0.4 volts and 0.5volts. This two step process enhances the soft programming of theover-erased cells with less operating current and better operatingefficiency requiring only approximately 200 ms for the entire repairprocess for the chip.

Turning to FIG. 7, a three level pull down driver circuit diagramincludingcircuit dimensions is used in combination with the circuit ofFIG. 8 to provide a word line driver for the two step embodiment of FIG.6.

The three level pull-down driver of FIG. 7 operates to control thesupply voltage at the node ZD2 701. The circuit has a first input atnode 702 anda second input at node 703. The first input at node 702 isthe enable soft program ENSPG pulse. The second input at node 703 is thecontrol signal SPG1 for indicating the first stage of the soft programalgorithm. The input at node 702 is connected to the gate of transistorM41, which has a width of 3 microns and a length of 1 micron. The drainof transistor M41 is connected to the supply VDD. The source oftransistor M41 is connected to the source and n-well of p-channeltransistor M42. This transistor is formed within a guard ring which isindicated by the asterisk. The gate and drain of transistor M42 arecoupled to node 701. The node 701 is also coupled to the drain ofn-channel transistor M43 which has a width of 250 microns and a lengthof about 0.8 microns. The source of transistor M43 isconnected toground.

Node 701 is also connected to the drain of n-channel transistor M47,havinga width of about 100 microns and a length of about 0.8 microns,and to the drain and gate of intrinsic n-channel transistor M44.Transistor M44 has awidth of about 350 microns and a length of about 1.6microns. The sources of transistors M47 and M44 are connected to thedrain of transistor M45. Transistor M45 has a width of about 15 micronsand a length of about 1.6 microns. The gate of transistor M45 isconnected to the node at the sourceof transistors M41 and M42. Thesource of transistor M45 is connected to ground 25.

The gate of transistor M43 is connected to the output of inverter 704,which has its input connected to the node 702 to receive the enable softprogram pulse.

As mentioned above, using the driver of FIG. 7, the node ZD2 can bedriven to three different levels. When the enable soft program pulse atnode 702 is low, transistor M41 is off and transistor M43 is on.Transistor M43 pulls the node ZD2 essentially to ground. During theenable soft program pulse, the node 702 is high. This turns ontransistor M41 and turns off transistor M43. When transistor M41 is on,the gate of transistor M45 is also pulled high turning M45 on. Also,when transistor M41 is on, transistor M42 is likewise on and pulls thegate of transistor M44 high turning on transistor M44. Thus, transistorsM44 and M45 pull-down node ZD2 to a level above ground and less thanabout 0.5 volts. When the input at node 703 is high, this also turns ontransistor M47, which further pulls down node ZD2 to a level of lessthan about 0.2 volts.

As mentioned above, the node 701 supplies the potential ZD2 to word linedrivers in the array. A representative word line driver shown in FIG. 8.It receives the ZD2 signal on node 701 as indicated. Other inputsinclude the output of decoders for the word lines, IN on node 801, VXPon node 802, and XR on node 805. Furthermore, a positive voltage supplyAVX is supplied on node 803. A negative voltage supply NVPP is suppliedon node 804. The level of the supply of these signals is controlled bysupply circuits, depending on the mode of operation of the circuit.Control signals PG1 and PG2 are used to select a voltage level for theword line 806 (WL).

When a signal IN and the signal XR are high, and the control signal PG1is low and the control signal PG2 is high, then the value of ZD2 at node701 is supplied to the word line.

The signal IN at node 801 is supplied to the source of n-channeltransistorM10 which has its gate connected to the decode signal XR onnode 805. The drain of transistor M10 is connected to node 825. Also,the drain of p-channel transistor M20 is connected to node 825. Thesource of transistor M20 and its n-well are connected to the supply AVXat node 803.When the control signal VXP on node 802 is low, node 825 ispulled high to the level of AVX. When VXP is high, transistor M20 is notinvolved in the circuit. Node 825 is connected to the gate of n-channeltransistor M22 andthe gate of p-channel transistor M21. The source andn-well of transistor M21 are connected to the supply AVX. The source oftransistor M22 is connected to the node 701 to receive the signal ZD2.

The node between the drains of transistors M21 and M22 is labeled 832.Node832 is connected through p-channel pass transistor M30 to the wordline at node 806. The n-well of the transistor M30 is connected to abias voltage AVW. The gate is connected to the control signal PG1. Node806 at the wordline is also connected through the p-channel passtransistor M31 to the negative supply NVPP at node 804. The n-well oftransistor M31 is connected to a bias voltage AVW. The gate oftransistor M31 is connected to the control signal PG2.

Using the circuit in FIG. 8, the WL 806 can obtain a voltage from theleft path (by transistor M30) or the right path (by transistor M31). Theleft path is mainly used to supply a positive very high voltage (VPPlevel, such as 12.6 volts) for programming, regular read voltage level(such as 5volts) two step voltages (such as the above described 0.1volts and 0.4 volts) for soft programming, or ground. The right path isused to supply anegative voltage (such as -7 volts).

During certain modes of operation, the AVX supply may be switched from aread potential at VDD level (as low as 4.4 volts) to a high programpotential VPP (as high as 12.6 volts). Also, the AVX changes states fromthe high program potential to the read potential. In this case, the ZD2line 701 will be pushed toward a negative voltage through M22.

By adding guard rings in the circuit of FIG. 7, it is possible toprevent alatch up problem caused by this negative push on ZD2. A wellstrapped p-substrate and n-well (so called "guard ring") may be used toavoid the latch-up problem. In such a case, guard rings (identified as adouble astrix next to M42 of FIG. 7, * *) are positioned on M42 forlatch up prevention. Also during the switch of AVX from a VPP level backto VDD level, a negative spike on ZD2 can damage M43, M44, M45 and M47.Thus, is preferable to put guard rings (identified as a single astrixnext to M43, M44, M45 and M47 of FIG. 7, *) on these transistors aswell.

FIG. 9 illustrates the circuitry for driving the top block selecttransistors, corresponding to the transistors 19 and 21 in FIG. 2, inorder to enable the soft program pulse of about 5.5 volts to get intothe buried drain lines, e.g. lines 10 and 11 of FIG. 2, on a sector bysector basis. The driver of FIG. 9 is used in connection with the sectorerase algorithm described in the above referenced U.S. Pat. No.5,414,664, whichis incorporated by reference as fully set forth herein.According to the sector erase algorithm described in such a patent, eachsector has associated with it a block erase flag. According to thepresent invention,a repair flag is set for sectors to be erased in thechip in addition to the block erase flag, and cleared after the softprogram cycle. Thus, according to one embodiment, four top block selectsignals (TBSEL of FIG. 2), which are used to decode four sets of localbit lines, each local bit line thirty-two word lines deep, in the array,share a single driver, suchas shown in FIG. 9. These four thirty-twoword line segments of the array correspond to a single sector. There isone flag per sector in this design.

The driver is connected to the top block select signal TBSEL on line 901(labelled TBSEL in FIG. 2), to pull it high during the soft programpulse for a selected sector. The signal is controlled by the sectorrepair flag in S-R flip-flop 904, and the enable soft program signalENSPG on line 903. The signal on line 902 is supplied at the output of acorresponding block erase flag register (not shown) and is connected tothe set-reset latch 904. This latch has a reset signal RESALL on line905 connected to the reset input. When the flag 902 goes high, the latch904 is set high, which enables the NAND gate 906 to switch in responseto the enable soft program signal on line 903. During an enable softprogram pulse, if the flag for the corresponding sector is set, then thesignal on line 907 is driven low. Else, the signal line 907 will be highfor unselected sectors.NAND gate 908 controls the block select signal online 901. During an enable soft program pulse on line 903, the NAND gate908 is controlled by the signal line 907 which is low for selectedsectors. Thus, a selected sector will have a high value at the output ofNAND gate 908. This is supplied through the pass gate 910 to the node901 driving the block select transistor. Pass gate 901 is an intrinsicdevice having a width of about 20 microns and a length of about 2microns.

Node 901 is coupled to the pull-up circuitry generally 911. The pull-upcircuitry generally 911 includes an n-channel transistor M48 (15 micronswide by 2 microns long) having its gate and drain connected to a highprogramming potential. The source of transistor M48 is connected to thedrain of transistor M42 (25 microns wide by 1.8 microns long) which hasits gate connected to node 901, and its source connected to node 912.Node912 is connected to the drain and gate of transistor M43, which hasits source connected to node 901. Transistor M43 is an intrinsic devicehavinga width of about 25 microns and a length of about 3 microns. Node912 is also connected to the gate of transistor M45 (3 microns wide by289.33 microns long) which is connected as a capacitor. The source anddrain of transistor M45 are connected to the clock signal on line 913.When node 901 is high under control of the NAND gate 908, transistor M42turns on, which results in pulling up node 901 to levels sufficient topass about 5.5 volts through the block select transistor to the burieddrain lines, when the clock signal 913 is enabled.

As indicated in the figure, a similar set of circuitry on the right sideisincluded, represented by the box 914. The RESALL signal on line 905 isasserted to reset all repair flags at the end of a soft program cycle.

Using the circuitry of FIGS. 7-9, all cells in the selected sectors areconnected simultaneously to the soft program pulse through the blockselect transistor decoding. The word lines in unselected sectors are ata low enough value that they do not disturb properly erased cells. Thusonlyselected sectors receive the program pulse through selected TBSELtransistors. Note that in this embodiment all of the wordlines (selectedor not) are driven to ground, 0.1 volts or 0.4 volts at the same time.It is the TBSEL transistors which are used to select the sectors beingrepaired. Further, selected sectors receive the pulse simultaneously.Thisensures that a fast soft program process for entire sectors or anentire array at once. Since the erased healthy cells are not disturbedduring thesoft program pulse, and leaky cells are limited to smallnumbers within a given sector, the operating current is controlled.Thus, soft programming is accomplished for selected sectors efficientlyand quickly, and repairs over-erased cells very well.

FIG. 10 is a graph showing the performance of the soft program pulse forover-erased cells which start out with a threshold of about negative onevolts along trace 1000, over-erased cells which start out with athresholdof about zero volts on trace 1001, healthy cells with athreshold of about 1.6 volts on trace 1002, and healthy cells with athreshold of about 2.2 volts on trace 1003. The chart shows the lengthof the soft programming pulse on logarithmic scale of seconds on thehorizontal axis, and the cellthreshold on the vertical axis.

As can be seen by traces 1002 and 1003, healthy cells are unaffected bya soft program pulse for as long as ten seconds, because the thresholdvoltages remain substantially constant over the entire graph. This istrueeven though the gate voltage on the trace 1003 is raised to about0.5 volts, illustrating that no significant disturbance of healthy cellsoccurs during the soft programming algorithm of the present invention.As can be seen with reference traces 1000 and 1001, where the drainvoltage is about 5 volts and the gate voltage is about 0.2 volts duringthe entirepulse, the traces converge into a region where the thresholdvoltage is about 1 volt after 200 milliseconds.

Accordingly, this invention provides repairing over-erased cellsblock-by-block and without a repair verify operation. Moreover, thisinvention includes applying a repair pulse, maintaining the word line atavoltage at ground or above, such as between approximately 0.1 volts and0.5volts. Moreover, this invention includes applying a repair pulse tothe erased cells in sequential two stages. In the first stage, the wordline voltage is maintained between approximately 0.1 volts and 0.2 voltsfor approximately 100 milliseconds. In the second stage, the word linevoltageis maintained between approximately 0.4 volts and 0.5 volts forapproximately 100 milliseconds.

The foregoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope oftheinvention be defined by the following claims and their equivalents.

What is claimed is:
 1. A floating gate memory integrated circuit,comprising:a set of floating gate memory cells arranged in a pluralityof rows and columns; a plurality of drain lines coupled to drainterminals of respective columns of cells in the set; a plurality ofsource lines coupled to source terminals of respective columns of cellsin the set; a plurality of word lines coupled to control gate terminalsof respective rows of cells in the set; a control circuit, coupled tothe pluralities of drain lines, source lines and word lines, for settingthreshold voltages of the cells in the set to a low threshold state,including voltage supply circuits to supply a voltage sequence to lowerthe thresholds of cells which results in some cells having thresholdslowered below a selected limit of threshold voltages, and then to supplya repair pulse during a repair time interval across the plurality ofsource lines and the plurality of drain lines, while setting the voltageon the plurality of word lines to a level below the selected limit. 2.The integrated circuit of claim 1, wherein said control circuit includescircuitry to pull the plurality of word lines substantially to groundduring the repair pulse.
 3. The integrated circuit of claim 1, whereinsaid control circuit includes circuitry to pull the plurality of wordlines to a level above ground but less than about one volt during therepair pulse.
 4. The integrated circuit of claim 1, wherein said controlcircuit includes circuitry to pull the plurality of word lines to alevel above ground but less that about 0.5 volts during the repairpulse.
 5. The integrated circuit of claim 1, wherein said controlcircuit includes circuitry to drive the plurality of word lines to afirst level during a first time interval and to a second level higherthan the first level during a second time interval within the repairpulse.
 6. The integrated circuit of claim 1, wherein the repair timeinterval lasts about 200 milliseconds.
 7. The integrated circuit ofclaim 5, wherein the repair time interval lasts about 200 milliseconds.8. The integrated circuit of claim 1, wherein the circuitry applies therepair pulse by driving the plurality of drain lines to a positivevoltage and driving the plurality of source lines to substantially aground potential.
 9. The integrated circuit of claim 1, wherein thecircuitry applies the repair pulse by driving the plurality of sourcelines to a positive voltage and driving the plurality of drain lines tosubstantially a ground potential.
 10. The integrated circuit of claim 1,including current limiting circuitry on at least one of the plurality ofdrain lines and the plurality of source lines.
 11. A floating gatememory integrated circuit, comprising:an array of floating gate memorycells arranged in a plurality of rows and columns including a pluralityof sectors, each sector including a plurality of drain lines coupled todrain terminals of respective columns of cells in the sector; aplurality of source lines coupled to source terminals of respectivecolumns of cells in the sector; and a plurality of word lines coupled tocontrol gate terminals of respective rows of cells in the sector; acontrol circuit, coupled to the pluralities of drain lines, source linesand word lines in the plurality of sectors, for setting thresholdvoltages of the cells in a selected sector to a low threshold state,including voltage supply circuits to supply a voltage sequence to lowerthe thresholds of cells in the selected sector which results in somecells having thresholds lowered below a selected limit of thresholdvoltages, and then to supply a repair pulse to the selected sector,during a repair time interval across the plurality of source lines andthe plurality of drain lines, while setting the voltage on the pluralityof word lines to a level below the selected limit.
 12. The integratedcircuit of claim 11, wherein said control circuit includes circuitry topull the plurality of word lines substantially to ground during therepair pulse.
 13. The integrated circuit of claim 11, wherein saidcontrol circuit includes circuitry to pull the plurality of word linesto a level above ground but less than about one volt during the repairpulse.
 14. The integrated circuit of claim 11, wherein said controlcircuit includes circuitry to pull the plurality of word lines to alevel above ground but less that about 0.5 volts during the repairpulse.
 15. The integrated circuit of claim 11, wherein said controlcircuit includes circuitry to drive the plurality of word lines to afirst level during a first time interval and to a second level higherthan the first level during a second time interval within the repairtime interval.
 16. The integrated circuit of claim 11, wherein therepair time interval lasts about 200 milliseconds.
 17. The integratedcircuit of claim 15, wherein the repair time interval lasts about 200milliseconds.
 18. The integrated circuit of claim 11, wherein thecircuitry applies the repair pulse by driving the plurality of drainlines to a positive voltage and driving the plurality of source lines tosubstantially a ground potential.
 19. The integrated circuit of claim11, wherein the circuitry applies the repair pulse by driving theplurality of source lines to a positive voltage and driving theplurality of drain lines to substantially a ground potential.
 20. Theintegrated circuit of claim 11, including current limiting circuitry onat least one of the plurality of drain lines and the plurality of sourcelines in the plurality of sectors.
 21. The integrated circuit of claim11, wherein the array includes a plurality of global bit lines, andsector drain select transistors coupling bit lines in the plurality ofbit lines with corresponding drain lines in the plurality of drain linesof a set of sectors in the array, and the circuitry supplies the repairpulse to the plurality of drain lines in the selected sector through thesector drain select transistors.
 22. The integrated circuit of claim 21,wherein the array includes a source supply line, and sector sourceselect transistors coupling the source supply line with the plurality ofsource lines of a set of sectors in the array, and the circuitrysupplies the repair pulse to the plurality of source lines in theselected sector through the sector source select transistors.
 23. In afloating gate integrated circuit having a memory array including aplurality of blocks of floating gate memory cells configured to beprogrammed and erased, wherein each of said cells has a drain, a sourceand a control gate, and wherein the control gates of said cells are incommunication with word lines, a method for erasing said programmedfloating gate memory cells, comprising the steps of:erasing cells;maintaining said word lines at a predetermined word line voltage level;generating a repair pulse having a repair voltage level; and during saidword line voltage maintaining step, applying said repair pulse toselected blocks of said plurality of blocks of floating gate memorycells independent of others of said plurality of blocks of floating gatecells: and wherein blocks in the plurality of blocks include cells fromat least two columns and cells from at least two rows.
 24. A method asrecited in claim 23, wherein repair pulse repairs over-erased cells sothat they may be reprogrammed absent a previously applied repair verifyoperation.
 25. A method as recited in claim 23, including maintainingsaid word line voltage level between approximately above ground and 0.5volts.
 26. A method as recited in claim 23, including:maintaining saidword line voltage level in two stages including a first, lower voltagestage and a second, higher voltage stage.
 27. A method recited in claim26, wherein during said first stage, said method includes:maintainingsaid word line voltage below approximately 0.2 volts.
 28. A method asrecited in claim 26, wherein during said second stage, said methodincludes:maintaining said word line voltage level between approximately0.3 volts and 0.5 volts.
 29. A floating gate integrated circuit,comprising:a memory array including floating gate memory cellsconfigured to be programmed and erased, wherein each of said cells has adrain, a source and a control gate, and wherein the control gates ofsaid cells are in communication with a word line capable of maintaininga word line voltage; control circuits, for erasing floating gate memorycells in the memory array, which generates an over-erased cell; and saidcontrol circuits further configured to generate a repair pulse, whereinsaid repair pulse across the sources and drain of floating gate memorycells, while a voltage on the word lines is provided in two stages, afirst stage in which the word line voltage is at a first lower voltagelevel, the second stage in which the word line voltage is at a secondhigher voltage level.
 30. A circuit as recited in claim 29, wherein saidfirst stage of the repair pulse is approximately 100 ms in duration andsaid second stage of said repair pulse which is approximately 100 ms induration.
 31. A circuit as recited in claim 29, wherein said controlcircuits are configured to maintain said word line voltage betweenapproximately above ground and 0.5 volts while said repair pulse isapplied to said erased cell.
 32. A circuit as recited in claim 29,wherein during said first stage, said word line voltage is betweenapproximately ground and about 0.2 volts.
 33. A circuit as recited inclaim 29, wherein during said second stage, said word line voltage isbetween approximately 0.3 volts and 0.5 volts.
 34. A floating gatememory integrated circuit, comprising:an array of floating gate memorycells arranged in a plurality of rows and columns including a pluralityof sectors, each sector including a plurality of drain lines coupled todrain terminals of respective columns of cells in the sector; aplurality of source lines coupled to source terminals of respectivecolumns of cells in the sector; and a plurality of word lines coupled tocontrol gate terminals of respective rows of cells in the sector; aplurality of sector flags indicating sectors of the array to be erasedin response to input signals; a control circuit, coupled to theplurality of sector flags, and to the pluralities of drain lines, sourcelines and word lines in the plurality of sectors, for setting thresholdvoltages of the cells in selected sectors indicated by the plurality ofsector flags to a low threshold state, including voltage supply circuitsto supply a voltage sequence to lower the thresholds of cells in theselected sector which results in some cells having thresholds loweredbelow a selected limit of threshold voltages, and then to supply arepair pulse to the selected sectors indicated by the plurality ofsector flags, during a repair time interval across the plurality ofsource lines and the plurality of drain lines, while setting the voltageon the plurality of word lines to a level below the selected limit. 35.The integrated circuit of claim 34, wherein said control circuitincludes circuitry to pull the plurality of word lines substantially toground during the repair pulse.
 36. The integrated circuit of claim 34,wherein said control circuit includes circuitry to pull the plurality ofword lines to a level above ground but less than about one volt duringthe repair pulse.
 37. The integrated circuit of claim 34, wherein saidcontrol circuit includes circuitry to pull the plurality of word linesto a level above ground but less that about 0.5 volts during the repairpulse.
 38. The integrated circuit of claim 34, wherein said controlcircuit includes circuitry to drive the plurality of word lines to afirst level during a first time interval and to a second level higherthan the first level during a second time interval within the repairtime interval.
 39. The integrated circuit of claim 34, wherein therepair time interval lasts about 200 milliseconds.
 40. The integratedcircuit of claim 38, wherein the repair time interval lasts about 200milliseconds.
 41. The integrated circuit of claim 34, wherein thecircuitry applies the repair pulse by driving the plurality of drainlines to a positive voltage and driving the plurality of source lines tosubstantially a ground potential.
 42. The integrated circuit of claim34, wherein the circuitry applies the repair pulse by driving theplurality of source lines to a positive voltage and driving theplurality of drain lines to substantially a ground potential.
 43. Theintegrated circuit of claim 34, including current limiting circuitry onat least one of the plurality of drain lines and the plurality of sourcelines in the plurality of sectors.
 44. The integrated circuit of claim34, wherein the array includes a plurality of global bit lines, andsector drain select transistors coupling bit lines in the plurality ofbit lines with corresponding drain lines in the plurality of drain linesof a set of sectors in the array, and the circuitry supplies the repairpulse to the plurality of drain lines in the selected sector through thesector drain select transistors, in response to the plurality of sectorflags.
 45. The integrated circuit of claim 44, wherein the arrayincludes a source supply line, and sector source select transistorscoupling the source supply line with the plurality of source lines of aset of sectors in the array, and the circuitry supplies the repair pulseto the plurality of source lines in the selected sector through thesector source select transistors, in response to the plurality of sectorflags.
 46. In a floating gate integrated circuit having a memory arrayincluding a plurality of blocks of floating gate memory cells configuredto be programmed and erased, wherein each of said cells has a drain, asource and a control gate, and wherein the control gates of said cellsare in communication with word lines, a method for erasing saidprogrammed floating gate memory cells, comprising the steps of:erasingcells; maintaining said word lines at a predetermined word line voltagelevel; generating a repair pulse having a repair voltage level; duringsaid word line voltage maintaining step, applying said repair pulse toselected blocks of said plurality of blocks of floating gate memorycells independent of others of said plurality of blocks of floating gatecells; and maintaining said word line voltage level betweenapproximately above ground and 0.5 volts.
 47. In a floating gateintegrated circuit having a memory array including a plurality of blocksof floating gate memory cells configured to be programmed and erased,wherein each of said cells has a drain, a source and a control gate, andwherein the control gates of said cells are in communication with wordlines, a method for erasing said programmed floating gate memory cells,comprising the steps of:erasing cells; maintaining said word lines at apredetermined word line voltage level; generating a repair pulse havinga repair voltage level; during said word line voltage maintaining step,applying said repair pulse to selected blocks of said plurality ofblocks of floating gate memory cells independent of others of saidplurality of blocks of floating gate cells; and maintaining said wordline voltage level in two stages including a first, lower voltage stageand a second, higher voltage stage.
 48. A method recited in claim 47,wherein during said first stage, said method includes:maintaining saidword line voltage below approximately 0.2 volts.
 49. A method as recitedin claim 47, wherein during said second stage, said methodincludes:maintaining said word line voltage level between approximately0.3 volts and 0.5 volts.
 50. A method as recited in claim 23, includinggenerating the repair pulse absent a previously applied repair verifyoperation.